Education

B.S. in Electrical Engineering Sep 2022 – Jun 2026
National Taiwan University
GPA: 4.09 / 4.30
Selected Coursework: Integrated Circuit Design, Introduction to Electronic Design Automation, Nanometer IC Physical Design (In Progress), SoC Verification (In Progress).
M.S. in Electronics Engineering Expected Enrollment: Sep 2026
National Taiwan University
Focus: Electronic Design Automation (EDA).

Undergraduate Research

Warpage Cost Integration for Global Floorplanning Feb 2025 – Dec 2025
Independent Study (I) | Advisor: Prof. Hui-Ru Jiang
  • Surveyed the warpage effect in chip physical design and systematically analyzed its severe physical impact on floorplanning.
  • Implemented robust warpage cost gradient computation in C within the established open-source ePlace framework.
  • Optimized wire length, electric force, and complex warpage metrics collaboratively to secure higher structural chip reliability.
Solving Real-World Problems with SAT Solvers Feb 2025 – Jul 2025
Independent Study (II) | Advisor: Prof. Chung-Yang Huang
  • Formulated the intricate "vocabulary learning set" optimization boundary mathematically, successfully establishing its NP-hard categorization.
  • Transformed constraints into reliable SAT evaluations, executing deep comparative solver benchmarks via BDD, PDR, and BMC schemas.

Internship Experience

Data Science Intern, Software Department Jun 2025 – Aug 2025
Lasertec Corporation
  • Refined core ResNet deep learning parameters for industrial defect inspection protocols over photomask interfaces.
  • Organized advanced computer vision routines to capture edge anomalies.

Major Competitions

CAD Contest 2025 Problem D Honorable Mention
APB Transaction Recognizer from VCD Waveforms
  • Developed a C++program to parse VCD waveforms and recognize APB transactions.
  • Implemented robust detection mechanisms to identify protocol violations, including out-of-range accesses, read/write overlaps, timeouts, and complex data/address mirroring.
ISPD 2026 Contest 1st Place
Post-Placement Buffering and Sizing
  • Architected advanced analytical post-placement buffering and gate sizing strategies to resolve complex timing and routing congestion challenges.
  • Built an efficient algorithm on GPU to speedup the process.

Skills & Competencies

Programming

C, C++, Python, Verilog, MATLAB

Domain

EDA algorithms, Digital IC Synthesis, SAT Solvers, ML pipelines

Extracurriculars

NTU EE Camp Instructor, Student Association lead

Languages

English (IELTS 7.0 Overall)